1. Field of the Invention
The present invention relates generally to an improved data processing system, and more specifically to controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power-performance efficiency of a simultaneous multi-threading data processing system.
2. Background Description
A symmetric multiprocessing (SMP) data processing system has multiple processors sharing global memory, where the operating system has a uniform view of all processors in the system. The operating system divides the work into tasks that are distributed among the various processors by dispatching one software thread of work to each processor at a time. Thus, a processor in an SMP system executes only one thread at a time.
A simultaneous multi-threading (SMT) processor is one that can concurrently execute more than one thread at a time. An SMP system can be made up of processors that support SMT or single-threaded mode of operation. An SMT system has the ability to favor one thread over another when both threads are running on the same processor. Simultaneous multithreaded processors often employ hardware or software mechanisms to control the priority of executing threads. Each processor in an SMT system can determine the priority of each thread that the processor is concurrently executing. The processor grants the thread that has the highest priority more decode units and more dispatch cycles, and makes other resources more available to that thread. Therefore, a higher priority thread will use more of the processor's resources and as a result do more work than the lower priority sibling threads on the same processor.
The objectives of controlling the priority of executing threads are typically to increase processor performance and maintain fairness across executing threads. Higher processor performance ensures higher utilization of processor resources, and fairness ensures that all executing threads are given equal opportunity and that no threads are forced to starve. The ability to control the flow of instructions in an SMT processor is important for performance improvements. When one thread is not making good progress, for performance reasons, the processor should allow another thread to have as much of the processor resources for the thread to make progress. There are several mechanisms built into microprocessors for controlling instruction flow as well as balancing work between threads. However, a consequence of existing thread priority control is excessive (and often avoidable or unnecessary) invocation of mechanisms such as balance flushes or dispatch flushes. While existing thread priority controls allow for increasing or maximizing processor performance, the inefficiencies caused by excessive or unnecessary flushes are a source of wasted power within multithreaded processors.